Members Only: Thin is In (July 2013)
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IEEE/CPMT Workshop in: Thin Is In:
Thin Chip & Packaging Technologies as Enablers for Innovations in the Mobility Era
Tuesday, July 9, 2013 at SEMICON West 2013
Electronic products, such as smart phones, tablets and other consumer products drive the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs. One of the key technologies to achieve these goals is thin 3D-packaging. Developments have lately been made with various embedding technologies, such as Fan out WLP and embedded devices. Higher integration levels and lower profiles are also achieved with wafer-level processes, at which most R&D is concentrated in the commercialization of 2.5D IC´s (with silicon interposer) & 3D ICs, as well as coreless substrate. Furthermore, there is tremendous pressure to decrease overall package height even with the additional dies stacking through innovation in wafer thinning, TSV, and ultrathin interconnects.
In this workshop, leaders from key segments of the eco-system shared their perspectives and experiences on what the future directions and emerging opportunities in the “Thin Packaging Technology” area will be and their readiness for commercialization.
Rolf Aschenbrenner, Fraunhofer IZM, Berlin and Jie Xue, Cisco
(Click on title to view presentation)