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Understanding Voids in Flip Chip Interconnects
- Webinar - Online
- Marsha Tickman – email@example.com
|Location||Local time||Time zone||UTC offset|
|New York (USA - New York)
||Wednesday, September 28, 2016 at 11:00:00 AM
|San Francisco (USA - California)
||Wednesday, September 28, 2016 at 8:00:00 AM
|Berlin (Germany - Berlin)
||Wednesday, September 28, 2016 at 5:00:00 PM
||Midnight between Wednesday, September 28, 2016 and Thursday, September 29, 2016
|Corresponding UTC (GMT)
||Wednesday, September 28, 2016 at 15:00:00
Pb-free solder is now ubiquitous throughout the packaging industry. Pb-freesolder interconnects dominate the high-end packaging interconnects: from large ball grid array (BGA) used on organic laminate to board connections, to flip chip joints on laminates, to micro-pillar forchipto Si on 2.5D or 3D interconnects But, how robust are these connections? Which defects are common and which can be avoided? This talk will cover one of the more common interconnect defects: solder voids. It will explain the root cause of solder voids occurring during structure fabrication, assembly and reliability stress, as well as detection methods and possible actions to prevent them.
Annual IEEE-SCV Soft Error Rate (SER) Workshops (Recordings and/or Presentations from Workshops held 2009-2014)
IEEE Santa Clara Valley CPMT Society Chapter Workshop (with Reliability and Electron Devices Chapters)
A unique forum for component manufacturers, assembly houses, and electronic system manufacturers to exchange innovative ideas and recent results on the measurement, monitoring, and control of alpha emission from packaging materials and manufacturing processes. Covers a wide range of areas and subjects critical to the control and mitigation of device soft error rates.
July 2013 at SEMICON West 2013
IEEE/CPMT Workshop in: Thin Is In: Thin Chip & Packaging Technologies as Enabler for Innovative Mobile Devices
July 2012 at SEMICON West 2012
CPMT Orange County Workshop, December 9, 2011, Newport Beach, CA. USA