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The CPMT Members Only area delivers technical content from a variety of sources to Society members -- as a membership benefit.  Content may include selected presentations from regional conferences, Chapter workshops,seminars and meetings; announcements of upcoming CPMT Webinars and recordings of past CPMT Webinars; and special offers.  View recordings (if available) and presentation files.

 

Upcoming Webinars

Probabilistic Design for Reliability in Electronics and Photonics July 19, 2017 11:00 AM EDT  Register 

Presenter: Ephraim Suhir

ABSTRACT

The recently suggested probabilistic design for reliability (PDfR) concept in electronics and photonics (EP)  is based on  1) highly focused and highly cost-effective failure oriented accelerated testing (FOAT),  aimed at understanding the physics of the anticipated failures and at quantifying, on the probabilistic basis, the outcome of  FOAT conducted for the most vulnerable element(s) of the product of interest for its most likely applications and the most meaningful combination of possible stressors (stimuli); 2) simple and physically meaningful predictive modeling (PM), both analytical and computer-aided, aimed at bridging the gap between the FOAT data and the most likely  operation conditions; and 3) subsequent FOAT-and-PM-based sensitivity analyses (SA) using the methodologies and algorithms developed as by-products at the two previous steps.  The PDfR concept proceeds from the recognition that nothing is perfect and that the difference between a highly reliable and an insufficiently reliable product is “merely” in the level of the probability of its failure. If this probability, evaluated for the anticipated loading conditions and the given time in operation, is not acceptable, SA can be effectively employed to determine what could/should be changed to improve the situation. The PDfR analysis enables one also to check if the product is not over-engineered, i.e., is not superfluously robust.  If it is, it might be too costly. The operational reliability cannot be low, but it does not have to be higher than necessary either. It has to be adequate for the given product and application. When reliability and cost-effectiveness are imperative, ability to optimize reliability is a must, and no optimization is possible if reliability is not quantified. It is shown also that the optimization of the total cost associated with creating a product with an adequate (high enough) reliability and acceptable (low enough) cost can be interpreted in terms of the adequate level of the availability criterion. The major PDfR concepts are illustrated by practical examples. We elaborate on the roles and interaction of analytical (mathematical) and computer-aided (simulation) modeling. It is shown also how the recently suggested powerful and flexible Boltzmann-Arrhenius-Zhurkov (BAZ) model and particularly its multi-parametric extension could be successfully employed to predict, quantify and assure operational reliability. The model can be effectively used to analyze and design EP products with the predicted, quantified, assured, and, if appropriate and cost-effective, even maintained and specified probability of operational failure. It is concluded that these concepts and methodologies can be accepted as an effective means for the evaluation of the operational reliability of EP materials and products, and that the next generation of qualification testing (QT) specifications and practices for such products could be viewed and conducted as a quasi-FOAT that adequately replicates the initial non-destructive segment of the previously conducted comprehensive full-scale FOAT. 

Past Webinars
 
 

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Understanding Voids in Flip Chip Interconnects

Date
2016-09-28
Location
Webinar - Online
Contact
Marsha Tickman – m.tickman@ieee.org
Description
 
LocationLocal timeTime zoneUTC offset
New York (USA - New York) Wednesday, September 28, 2016 at 11:00:00 AM EDT UTC-4 hours
San Francisco (USA - California) Wednesday, September 28, 2016 at 8:00:00 AM PDT UTC-7 hours
Berlin (Germany - Berlin) Wednesday, September 28, 2016 at 5:00:00 PM CEST UTC+2 hours
Tokyo (Japan) Midnight between Wednesday, September 28, 2016 and Thursday, September 29, 2016 JST UTC+9 hours
Corresponding UTC (GMT) Wednesday, September 28, 2016 at 15:00:00
 
Pb-free solder is now ubiquitous throughout the packaging industry. Pb-freesolder interconnects dominate the high-end packaging interconnects: from large ball grid array (BGA) used on organic laminate to board connections, to flip chip joints on laminates, to micro-pillar forchipto Si on 2.5D or 3D interconnects   But, how robust are these connections? Which defects are common and which can be avoided?  This talk will cover one of the more common interconnect defects: solder voids.  It will explain the root cause of solder voids occurring during structure fabrication, assembly and reliability stress, as well as detection methods and possible actions to prevent them. 

 

Technical Presentations

 
Annual IEEE-SCV Soft Error Rate (SER) Workshops (Recordings and/or Presentations from Workshops held 2009-2014)
IEEE Santa Clara Valley CPMT Society Chapter Workshop (with Reliability and Electron Devices Chapters) 
A unique forum for component manufacturers, assembly houses, and electronic system manufacturers to exchange innovative ideas and recent results on the measurement, monitoring, and control of alpha emission from packaging materials and manufacturing processes. Covers a wide range of areas and subjects critical to the control and mitigation of device soft error rates.
 

July 2013 at SEMICON West 2013

IEEE/CPMT Workshop in: Thin Is In: Thin Chip & Packaging Technologies as Enabler for Innovative Mobile Devices
July 2012 at SEMICON West 2012

CPMT Orange County Workshop, December 9, 2011, Newport Beach, CA. USA