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CPMT Webinar: Photonics in Heterogeneous 3D-SiP: A Key to Maintaining the Pace of Progress
- 2016-02-04 - 2016-02-04
- Webinar - Online
- Marsha Tickman – email@example.com
The world of electronics is changing with 3 new driving forces that will define the future emerging simultaneously:
- The end of Moore’s Law scaling for CMOS is approaching
- The internet of things has new requirements for data sources and network connectivity
- Data, logic and applications are migrating to the Cloud
Each of these forces contributes to difficult challenges that must be overcome to maintain the pace of progress. The primary technical challenges are cost per function, power per function and physical density of bandwidth. The solutions cannot come from CMOS in the future as power, cost and bandwidth density are all approaching their limits in CMOS. The future technical challenges for data storage, movement and analysis will all depend on moving system components closer together and interconnecting systems with low cost, low power, low latency networks. Most, if not all, of the components are known but a new generation of packaging technology is required to integrate these components into cost reduced power efficient system level products. The requirements can be met through heterogeneous integration in 3D-SiP architectures. These SiP products will require integration of electronic, photonic and plasmonic devices into the package.
The networks required will use photonics to move the photons closer the electronics and dramatically increase the number of interconnections to reduce the power and latency of data communication. Today photons are moving to PCBs but in the future they will be at individual package and perhaps even to the individual integrated circuits.
Power and cost reductions of 10,000 times will be needed during the next 15 years. New architectures, new devices, new materials and new manufacturing processes for packaging and system to system networking will be required. Photonics as the key enabler will be discussed.
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Annual IEEE-SCV Soft Error Rate (SER) Workshops (Recordings and/or Presentations from Workshops held 2009-2014)
IEEE Santa Clara Valley CPMT Society Chapter Workshop (with Reliability and Electron Devices Chapters)
A unique forum for component manufacturers, assembly houses, and electronic system manufacturers to exchange innovative ideas and recent results on the measurement, monitoring, and control of alpha emission from packaging materials and manufacturing processes. Covers a wide range of areas and subjects critical to the control and mitigation of device soft error rates.
July 2013 at SEMICON West 2013
IEEE/CPMT Workshop in: Thin Is In: Thin Chip & Packaging Technologies as Enabler for Innovative Mobile Devices
July 2012 at SEMICON West 2012
CPMT Orange County Workshop, December 9, 2011, Newport Beach, CA. USA