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Probabilistic Design for Reliability in Electronics and Photonics July 19, 2017 11:00 AM EDT Register
Presenter: Ephraim Suhir
The recently suggested probabilistic design for reliability (PDfR) concept in electronics and photonics (EP) is based on 1) highly focused and highly cost-effective failure oriented accelerated testing (FOAT), aimed at understanding the physics of the anticipated failures and at quantifying, on the probabilistic basis, the outcome of FOAT conducted for the most vulnerable element(s) of the product of interest for its most likely applications and the most meaningful combination of possible stressors (stimuli); 2) simple and physically meaningful predictive modeling (PM), both analytical and computer-aided, aimed at bridging the gap between the FOAT data and the most likely operation conditions; and 3) subsequent FOAT-and-PM-based sensitivity analyses (SA) using the methodologies and algorithms developed as by-products at the two previous steps. The PDfR concept proceeds from the recognition that nothing is perfect and that the difference between a highly reliable and an insufficiently reliable product is “merely” in the level of the probability of its failure. If this probability, evaluated for the anticipated loading conditions and the given time in operation, is not acceptable, SA can be effectively employed to determine what could/should be changed to improve the situation. The PDfR analysis enables one also to check if the product is not over-engineered, i.e., is not superfluously robust. If it is, it might be too costly. The operational reliability cannot be low, but it does not have to be higher than necessary either. It has to be adequate for the given product and application. When reliability and cost-effectiveness are imperative, ability to optimize reliability is a must, and no optimization is possible if reliability is not quantified. It is shown also that the optimization of the total cost associated with creating a product with an adequate (high enough) reliability and acceptable (low enough) cost can be interpreted in terms of the adequate level of the availability criterion. The major PDfR concepts are illustrated by practical examples. We elaborate on the roles and interaction of analytical (mathematical) and computer-aided (simulation) modeling. It is shown also how the recently suggested powerful and flexible Boltzmann-Arrhenius-Zhurkov (BAZ) model and particularly its multi-parametric extension could be successfully employed to predict, quantify and assure operational reliability. The model can be effectively used to analyze and design EP products with the predicted, quantified, assured, and, if appropriate and cost-effective, even maintained and specified probability of operational failure. It is concluded that these concepts and methodologies can be accepted as an effective means for the evaluation of the operational reliability of EP materials and products, and that the next generation of qualification testing (QT) specifications and practices for such products could be viewed and conducted as a quasi-FOAT that adequately replicates the initial non-destructive segment of the previously conducted comprehensive full-scale FOAT.
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CPMT Webinar: Photonics in Heterogeneous 3D-SiP: A Key to Maintaining the Pace of Progress
- 2016-02-04 - 2016-02-04
- Webinar - Online
- Marsha Tickman – email@example.com
The world of electronics is changing with 3 new driving forces that will define the future emerging simultaneously:
- The end of Moore’s Law scaling for CMOS is approaching
- The internet of things has new requirements for data sources and network connectivity
- Data, logic and applications are migrating to the Cloud
Each of these forces contributes to difficult challenges that must be overcome to maintain the pace of progress. The primary technical challenges are cost per function, power per function and physical density of bandwidth. The solutions cannot come from CMOS in the future as power, cost and bandwidth density are all approaching their limits in CMOS. The future technical challenges for data storage, movement and analysis will all depend on moving system components closer together and interconnecting systems with low cost, low power, low latency networks. Most, if not all, of the components are known but a new generation of packaging technology is required to integrate these components into cost reduced power efficient system level products. The requirements can be met through heterogeneous integration in 3D-SiP architectures. These SiP products will require integration of electronic, photonic and plasmonic devices into the package.
The networks required will use photonics to move the photons closer the electronics and dramatically increase the number of interconnections to reduce the power and latency of data communication. Today photons are moving to PCBs but in the future they will be at individual package and perhaps even to the individual integrated circuits.
Power and cost reductions of 10,000 times will be needed during the next 15 years. New architectures, new devices, new materials and new manufacturing processes for packaging and system to system networking will be required. Photonics as the key enabler will be discussed.
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Annual IEEE-SCV Soft Error Rate (SER) Workshops (Recordings and/or Presentations from Workshops held 2009-2014)
IEEE Santa Clara Valley CPMT Society Chapter Workshop (with Reliability and Electron Devices Chapters)
A unique forum for component manufacturers, assembly houses, and electronic system manufacturers to exchange innovative ideas and recent results on the measurement, monitoring, and control of alpha emission from packaging materials and manufacturing processes. Covers a wide range of areas and subjects critical to the control and mitigation of device soft error rates.
July 2013 at SEMICON West 2013
IEEE/CPMT Workshop in: Thin Is In: Thin Chip & Packaging Technologies as Enabler for Innovative Mobile Devices
July 2012 at SEMICON West 2012
CPMT Orange County Workshop, December 9, 2011, Newport Beach, CA. USA