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Distinguished Lecturer Program

CPMT Vice President, Education: Jean Trewhella     

CPMT Distinguished Lecturers are selected from among¬† CPMT Fellows, Award winners, and Society leaders, who are members of the technical community and experts in their field.¬† They are available to present lectures and/or courses at CPMT Society events ‚Äď Chapters, Conferences, Workshops or Symposia; as well as IEEE Student Chapter events.¬† CPMT Chapter events are given priority.

The CPMT Society may provide travel assistance directly to the Lecturer when requested and approved. Availability is determined by the Lecturer, based on his/her schedule.  All events must receive approval from the CPMT VP, Education prior to final commitment.

The CPMT Distinguished Lecturer Program (DLP) aims at serving communities interested in the scientific, engineering, and production aspects of materials, component parts, modules, hybrids and micro-electronic systems for all electronic applications.

Lecturers will tailor their presentations to the intended audience. The DLP strives to support CPMT Chapters worldwide by helping them to invite leading researchers in their respective fields and IEEE Student Chapters to encourage students to pursue CPMT related fields and to join the CPMT society. The DLP talk is a major event in the life of the inviting Chapter.

Requests for lectures given by one of the CPMT Distinguished Lecturers (DL) must be submitted by the Chapter Chairs or the Conference/Workshop/Symposium Chair to the CPMT VP, Education, copying the CPMT Society Executive Director according to the procedure described below.

DL Program Guidelines, Policies, Procedures

DL Program Request Form


CPMT Distinguished Lecturers

Avram Bar-Cohen, Ph.D.
Department of Mechanical Engineering
University of Maryland
College Park, Maryland  USA
Phone: 301-405-3173
Email: abc@umd.edu
Topics: Thermal packaging

Moises Cases
The Cases Group, LLC
Austin, Texas, U.S.A.
Email: moises@thecasesgrp.com

Topics:  Signal and power distribution integrity for complex high-speed multiple board system designs; Modeling, simulation and verification of integrated circuits, electronic packages and system interconnect technologies; High-speed and low powers systems interconnect design methodology and tools; Digital system electrical designs, timings and integration; High-speed I/O architectures and designs; Service science management and engineering applied to engineering services

Rajen Chanchani, Ph.D.
Albuquerque, NM USA
Phone: 505-275-1260
Email: rajen505@aol.com
Topics: 3D Integration, Advanced Substrates
 
William T. Chen, Ph.D.
ASE (U.S.) INC
Santa Clara, CA  USA
Cell: 408-250-4290
william.chen@aseus.com
Topics: Semiconductor and Electronics Industry Trends and Roadmap
 
Badih El-Kareh, Ph.D.
PIYE Company
Cedar Park, Texas  USA
Phone: 512-219-9104
Email: bek@ieee.org
Topics: Semiconductor devices physics, reliability and processing
 
Xuejun Fan, Ph.D.
Department of Mechanical Engineering
Lamar University
Beaumont TX USA
Phone: 409-880-7792
Email: xuejun.fan@lamar.edu
Topics: Design, modeling and reliability in micro-/nano- electronic packaging and microsystems
 
Paul D. Franzon, Ph.D.
NC State University
ECE
Raleigh, NC  USA
Tel.: 919-515-7351
Email: paulf@ncsu.edu
Topics: 3DIC and 3D Packaging Application,Design and CAD; I/O Macromodeling, including IBIS; High-Speed, Low Power Chip to Chip Communications
 
Philip Garrou, Ph.D.
Microelectronic Consultants of North Carolina
Research Triangle Park, NC USA
Phone: 919-604-7798
Email: philgarrou@att.net
Topics: Thin film technology; IC packaging and interconnect; Microelectronic materials; 3D-IC integration
 
R. Wayne Johnson, Ph.D.
Electrical and Computer Engineering Department
Tennessee Tech University
Cookeville, TN USA
Phone: 931-372-3430
Email: wjohnson@tntech.edu
Topics: Extreme Environment Electronics
 
George A. Katopis, Ph.D.
IBM Corporation, Systems Group
Poughkeepsie, NY  USA
Phone: 845-435-6719
Email: katopis@us.ibm.com
Topics: Signal integrity issues including electronic noise; Electrical modeling of packaging structures
 
John H. Lau, Ph.D.
Hong Kong University of Science and Technology
Clear Water Bay, Kowloon, Hong Kong
Email: johnlau@ust.hk
Topics: Electronics and Photonics 2D and 3D packaging and manufacturing
                                            
Ning-Cheng Lee, Ph.D.
Indium Corporation of America
Clinton, NY USA
Phone: +1 (315) 381-7613
Email: nclee@indium.com
Topics: Lead-free soldering including solderalloys, surface finishes, components, substrates, and other materials; Processes,reliability, failure modes, and troubleshooting;Advanced applications including packaging, and ultra-fine pitch applications
 
S. W. Ricky Lee, Ph.D.
Center for Advanced Microsystems Packaging
Hong Kong University of Science and Technology
Clear Water Bay, Kowloon, Hong Kong
Tel: +852-23587203
Email: rickylee@ust.hk
Topics: Solder Joint Reliability, 3D IC Integration, and LED Packaging
 
Johan Liu, Ph.D.
SMIT Center and Bionano Systems Laboratory
Chalmers University of Technology
Gothenburg, Sweden
Phone: +46-31-772 3067
Email: jliu@chalmers.se
Topics: Micro and nano-electronic electrically conductive adhesives
 
James E. Morris, Ph.D.
Department of Electrical and Computer Engineering
Portland State University
Portland, Oregon USA
Phone: 503-725-9588
Email: jmorris@cecs.pdx.edu
Topics: Electrically conductive adhesives; Electronics packaging; Nanotechnologies
 
Kyung W. Paik, Ph.D.
Korea Advanced Institute of Science & Technology
KAIST Dept. of MS&E
Daejon, Korea
Phone: 82-42-869-3335
E-mail: kwpaik@kaist.ac.kr
Topics: Electrically conductive adhesives (ACF, NCF,ACP, NC)
 
Michael Pecht, Ph.D.
University of Maryland
CALCE Electronic Products and Systems Center
College Park, MD  USA
Phone: 301-405-5323
Email: pecht@calce.umd.edu
Topics: Prognostics and reliability of electronic products and systems

Eric D. Perfecto
IBM Corporation ‚Äď Systems & Technology Groups
Hopewell Jct., NY USA
Email:  perfecto@us.ibm.com

Topics: Fine pitch interconnect, chip to chip and chip to laminate connection, UBM and solder selection, chip package interaction and 2.5D fabrication

Karl J. Puttlitz, Ph.D.
Puttlitz Engineering Consultancy, LLC
Wappingers Falls, NY USA
Phone: 845-297-0716

Topics: Flip Chip Issues/Technology; Area Array(1st & 2nd Level) Issues/Technology; Lead-free Issues/Technology

Dongkai Shangguan, Ph.D.
San Jose, CA
Phone: 408-646-5121
E-Mail: dksg@ieee.org
Topics: Materials, reliability, lead-free, microelectronics packaging, board assembly, electronics manufacturing

 

Nihal Sinnadurai, Ph.D.
Suffolk IP11 9RZ UK
Mobile: +44 7803 182769
email: sinnadurai@aol.com
Topics: Accelerated Ageing for Reliability Assurance -theory and practical methods - including HAST (my invention originally); The use of encapsulation and plastic packaging and reliability evaluation method; PCB & Hybrid technologies; Thermal management and design

Ephraim Suhir, Ph.D.
Los Altos, CA 94024 USA
Tel.: 650-969-1530
Email: suhire@aol.com
Topics: Accelerated life testing; Probabilistic physical
design for reliability; Bonded assemblies; Thermal stress; Predictive modeling; Fiber optics structures: design for reliability; Dynamic response to shocks and vibrations
 
Yutaka Tsukada, Ph.D.
IPP-iPACKS representative
Bodaiji, Konan-city, Shiga-pref Japan
Phone: 81-90-5602-8324
Email: yutsukada@aol.com
Topics: Flip Chip Technologies on organic substrates, low temperature joining, barriers and future direction; Built-up Substrate Technologies, fine pitch line fabrication, barriers, and future direction
 
Rao Tummala, Ph.D.
Microsystems Packaging Research
Center (PRC)
Georgia Institute of Technology
Atlanta, GA USA
Tel.: 404-894-9097
Email: rao.tummala@ece.gatech.edu
Topics: Electronics Packaging
 
Walter Trybula, Ph.D.
Trybula Foundation, Inc.
Austin, TX  USA
Tel.: 512.356.3306
Nanomaterials Application Center Texas State University
San Marcos, TXUSA
Email: w.trybula@ieee.org
Topics: Emerging Technology, Advanced Lithography, Nanotechnology, Nano manufacturing, Nanomaterials, Environmental issues of Nanotechnology, Business Requirements of Nanotechnology
 
E. Jan Vardaman
TechSearch International, Inc.
Austin, TX USA
Phone: 512-372-8887
Email: jan@techsearchinc.com
Topics: International developments in semiconductor packaging, manufacturing and assembly; SiP: Business and technology Trends; drivers in advanced packaging; Flip chip and wafer level packaging
 
Paul Wesling
Saratoga, CA USA
Tel.:408-320-1105
Email: p.wesling@ieee.org
Topics: Using Xplore, and Google Scholar to Mine IEEE's On-line Repository of Technical Information; Origins of Silicon Valley and the CPMT Society
 
Ralph W. Wyndrum Jr., Ph.D.
Executive Engineering Consultants
Fair Haven , NJ USA
Phone: 732-219-0005
Email: r.wyndrum@ieee.org
Topics: Alternative energy and energy avoidance; Innovation issues

 

Jie Xue
Cisco Systems, Inc
San Jose, CA, USA
Email:  jixue@cisco.com
Topics:  Advanced Packaging for Networking Application;  Impact of Internet of Everything (IoE) to Semiconductor Industry eco-system;    High performance substrate technologies;   Trends and challenges of Silicon Photonics for datacenter and networking applications
 
Kishio Yokouchi, Ph.D.
Fujitsu Interconnect Technologies Ltd.,
Nagano City, Nagano, Japan
Phone: +81-26-263-2711
Email: kyokouchi@jp.fujitsu.com
Topics: Thermal management technologies; Embedded passive component technologies; Chip to chip optical interconnection technologies