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CPMT Member-at-Large Bios

Bios: CPMT Board of Governors Members-at-Large 2012-2014

 

AVRAM BAR-COHEN (M’85,SM’87,F’93) Dr. Avram Bar-Cohen is an internationally recognized leader in thermal science and technology, an Honorary member of ASME, and Fellow of IEEE, as well as Distinguished University Professor in the Department of Mechanical Engineering at the University of Maryland. His publications, lectures, short courses, and research outcomes, as well as professional service in ASME and IEEE, have helped to create the scientific foundation for the thermal management of electronic components and systems and pioneered techniques for energy-efficient sustainable design of manufactured products. His current research focuses on on-chip thermoelectric and two-phase microchannel coolers for high heat flux electronic components, thermal control of solid-state lighting systems, and polymer-fiber composite heat exchangers for seawater applications. Bar-Cohen was the general chair for the 2010 International Heat Transfer Conference in Washington DC and is the President of the Assembly of International Heat Transfer Conferences. He is the Editor-in-Chief of World Scientific Press’ forthcoming Encyclopedia of Thermal Packaging. From 2001 to 2010 he served as the Chair of Mechanical Engineering at Maryland and is currently on assignment as a Program Manager in the Microsystem Technology Office at the Defense Advanced Projects Agency in Virginia.

In addition to Honorary membership in ASME, Bar-Cohen’s honors include the Luikov Medal from the International Center for Heat and Mass Transfer in Turkey (2008),  ASME’s Heat Transfer Memorial Award (1999), Curriculum Innovation Award (1999),  Edwin F. Church Medal (1994) and  Worcester Reed Warner Medal (2000), and the Electronic and Electrical Packaging Division’s Outstanding Contribution Award (1994) as well as the InterPack Achievement Award (2007).  Bar-Cohen was the founding chair of the IEEE Intersociety Conference on Thermal Management in Electronic Equipment (ITHERM) in 1988 and was recognized with the IEEE CPMT Society’s Outstanding Sustained Technical Contributions Award (2002), the ASME/IEEE ITHERM Achievement Award (1998) and the THERMI Award from the IEEE/Semi-Therm Conference (1997).

Bar-Cohen has co-authored Design and Analysis of Heat Sinks (Wiley, 1995) and Thermal Analysis and Control of Electronic Equipment (McGraw-Hill, 1983), and has co-edited 14 books in this field.  He has authored/co-authored some 350 journal papers, refereed proceedings papers, and chapters in books; has delivered 70 keynote, plenary and invited lectures at major technical conferences and institutions, and he holds 8 US and 3 Japanese patents. He has advised to completion 60 master’s and Ph.D. students at the University of Maryland, the University of Minnesota and the Ben Gurion University (Beer Sheva, Israel), where he began his academic career in 1972. From 1998-2001 he directed the University of Minnesota Center for the Development of Technological Leadership and held the Sweatt Chair in Technological Leadership.

DARVIN R. EDWARDS (M’87,SM’10) Mr. Darvin R. Edwards received the B.S. degree in Physics from Arizona State University, Tempe, AZ in 1980.  After joining Texas Instruments Incorporated in 1980, he developed integrated test structures such as strain gauges, moisture sensors, thermal sensors, and structures to determine the impact of package stresses on IC thin film layers.  He developed a set of IC design rules for packaging which has been continuously updated and is still in use today.  He then worked to build TI’s competence in thermal characterization and thermal management.  Elected TI Fellow in 1999, he is presently manager of the Advanced Package Modeling and Characterization group which is responsible for thermal, electrical, and stress analysis for a wide range of product families, as well as ensuring successful qualification and introduction of products to the market.  Packages and technologies he has helped develop include TSV, POP, MCM, FC-BGA, PBGA, QFN, WCSP, QFP, and SOICs.  He is currently chair of the SRC GRC Interconnect and Packaging Sciences’ Science Area Coordinating Committee, and works regularly with universities to coordinate TI’s packaging research interests.  Professional activities have included over 25 years of service on the Applied Reliability program selection committee of the ECTC, authoring 5 JEDEC standards, and serving as an industrial liaison on multiple SRC projects.  Mr. Edwards has authored and co-authored over 45 papers in the field of IC packaging, has written two book chapters, and holds 20 US patents.

BETH KESER (M’99,SM’10) has over 15 years experience in the semiconductor industry. Beth received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. in Materials Science and Engineering at the University of Illinois at Urbana-Champaign. Beth’s interests include developing revolutionary materials and packaging technologies for the semiconductor industry resulting in 7 patents, 5 patents pending, and over 33 publications in this area. Currently, Beth is the Wafer Level Packaging Product and Technology Manager at Qualcomm in San Diego. Her team and co-authors just presented 3 papers on their work on advancements in wafer level packaging at the 61^st ECTC in Orlando.

Before joining Qualcomm in 2009, Beth Keser was instrumental in developing 2 packaging technologies during her career at Motorola and Freescale Semiconductor. Beth led the Wafer-Level Chip Scale packaging team at Motorola, which included directing the activities of process engineering, package characterization, package reliability, and mechanical modeling.  Beth developed an innovative new double-bump structure where the first bump on the wafer was encapsulated with a photoimageable, filled stress compensation layer. Beth is a co-inventor on this invention US Patent. Also, to improve ball attach method for the first ball and second ball for the WL-CSP technology a new super-saturated flux was designed. Beth is a co-inventor of this invention US Patent. In addition, Beth and her co-inventors created a new under bump metallurgy specifically for this WL-CSP and had it patented.

In addition, Beth Keser was the lead technologist and manager of the Redistributed Chip Packaging Technology (RCP). Beth led the team that developed this technology for 6 years. Beth developed several process and material solutions for this new technology. Beth has filed 6 patents on this technology. Her team had 10 patents granted and 10 other patents filed. Beth presented RCP at the Phoenix local chapter of IEEE WAD and CPMT meetings, as well as at the Phoenix local MEPTEC luncheon. In addition, 2 papers were published at ECTC on RCP.

Beth is an IEEE Senior Member whose volunteer activities and professional society responsibilities include: ECTC Executive Committee 2010-present, 2012 ECTC Assistant Program Chair, ECTC Advanced Packaging Sub-committee member 2000-present, IMAPS Device Packaging Conference Technical Chair 2006-2009, IMAPS Flip Chip/CSP Sub-committee member 2000-2009, chair 2005-2008, SMTA’s International WLP Conference WLP Track Chair 2010-2011.

Beth has been very active in IEEE CPMT’s ECTC conference both as a volunteer and as a technical contributor. Beth has presented 4 papers at ECTC (2001, 2007 and 2011) and co-authored 5 other papers (2000, 2003, 2008, and 2011).

C. P. WONG (SM’87,F’92) Prof. C. P. Wong is currently Dean of the Faculty of Engineering at the Chinese University of Hong Kong. He is on a no pay leave from the Georgia Institute of Technology(GT) where he is a Regents’ Professor and the Charles Smithgall Institute- Endowed Chair at the School of Materials Science and Engineering. He received his B.S. degree from Purdue University, and his MS. and Ph.D. degrees from the Pennsylvania State University. After his doctoral study, he was awarded a two-year postdoctoral fellowship with Nobel Laureate Professor Henry Taube at Stanford University.  Prior to joining GT in 1996, he was with AT&T Bell Laboratories for many years and became an AT&T Bell Laboratories Fellow in 1992 for his seminal contributions to low-cost high-performance packaging of semiconductor devices and components.

His research interests lie in the fields of polymeric electronic materials, electronic, photonic and MEMS packaging and interconnect, interfacial adhesions, nano-functional material syntheses and characterizations, nano-composites, such as well-aligned carbon nanotubes, graphenes,  high performance electrical conductive adhesives, ultra high k capacitor composites, lead-free alloys, flip chip underfills, and novel lotus effect coating materials.

He received many awards, among those, the AT&T Bell Labs Fellow Award in 1992 (the most prestigious Technical Award bestowed by Bell Labs), the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society Outstanding Sustained Technical Contributions Award in 1995, the IEEE Third Millennium Medal in 2000, the IEEE Educational Activities Board Outstanding Education Award in 2001, the IEEE CPMT Society Exceptional Technical Contributions Award in 2002, the Georgia Tech Class 1934 Distinguished Professor Award (the highest award bestowed by GT to a faculty) in 2004, named holder of the Charles Smithgall Institute-Endowed Chair Professor (holder of one of the two GT Institute-Endowed Chairs) in 2005, the GT Outstanding BS and PhD Thesis Advisor Awards, the IEEE Components, Packaging and Manufacturing Technology  Field Award in 2006 (hailed by the IEEE as “Father of Modern Semiconductor Packaging”), the Sigma Xi’s Monie Ferst Outstanding Educational Award in 2007, the Society of Manufacturing Engineers’ Total Excellence in Electronic Manufacturing Award in 2008 and the IEEE CPMT David Feldman Award and the Pennsylvania State University Distinguished Alumni Award in 2009.

Prof. Wong served as CPMT Society President in 1992 and 1993, and is currently Chair of the CPMT Society Fellow Evaluation Committee.  He holds over 50 U.S. patents, and has published over 1,000 technical papers, co-authored and edited 10 books and is a member of the National Academy of Engineering of the USA since 2000.

MERVI PAULASTO-KRÖCKEL  (M’09) Dr. Mervi Paulasto-Kröckel is currently working as a professor at the Aalto University* School of Electrical Engineering in the Department of Electronics. She has broad experience in microelectronics packaging development specifically for automotive and power electronics market. Before transferring into the academic world in 2008, she worked over 12 years in the semiconductor industry in various R&D and management positions.

Paulasto-Kröckel began her studies at the Helsinki University of Technology in 1985. She studied materials science and engineering as her major and semiconductor technology as minor. After graduation as Master of Science in Technology in 1990 she continued her studies in the Technical Universities of Aachen (RWTH Aachen) and Helsinki and attained her doctroral degree in 1995.

After a 2-years post-doctoral appointment at the Joint Research Centre of European Commission in the Netherlands, her professional career continued in the electronics industry. In 1996, she moved to Munich, Germany where she started at Motorola Semiconductor Products Sector in a new team focusing on automotive electronics development. At Motorola she worked on several research and development assignments including flip chip process development and technology transfer to manufacturing. Her career took a new direction when she was invited to lead the packaging development of Infineon Automotive Power in 2004. At Infineon Technologies she was promoted to Director Package Development responsible for semiconductor assembly and interconnect development for automotive products worldwide. In this role she was responsible for over 10 M€ development budget and 50+ varying size projects interfacing with a large matrix organization of business managers, product and technology developers.

In the fall 2008 Paulasto-Kröckel was selected to become the successor of her former supervisor, professor Jorma Kivilahti. She moved with her Finnish-German family to Finland end of 2008, and is now chairing Electronics integration and reliability as well as Bioadaptive technology in Aalto University. Her research focus is on materials compatibility in electronics and MEMS, implantable electronics, interconnect technologies, multimaterial assemblies behavior under different loads and their characteristic failure modes and mechanisms. Her research group is heading several academic research projects, but has also a broad cooperation with major electronics companies.

Prof. Paulasto-Kröckel has over 40 international publications in fields of microelectronics packaging and interfacial compatibility of dissimilar materials. She is member of IEEE/CPMT and has participated in technical programme committees, chairing sessions and giving key note lectures in several IEEE CPMT conferences including ESTC, EPTC, APM, EuroSimE, IEMT, ASTR as well as IEEE ESSDERC conference.  She is also a member of the board of Okmetic, Finnish based wafer manufacturing company. Recently, she was selected to become a member of Finnish Academy of Technical Sciences.

 

*Aalto University is a new university created from a high-profile merger between three leading universities in Finland – the Helsinki University of Technology, the Helsinki School of Economics and the University of Art and Design.

MASAHIRO AOYAGI (M’94,SM’10) received the Bachelor of Engineering in Electronic Engineering from Nagoya Institute of Technology, Nagoya, Japan, in 1982; and the Doctor of Engineering degree in Electronic Engineering from Nagoya Institute of Technology, in 1992. 

He joined Electrotechnical Laboratory (ETL), Tsukuba, Japan  in 1982, where he was engaged in the research and development of Nb, NbN superconducting devices and Josephson integrated circuits until 1994, for establishing Josephson Computer Technology.  He was engaged in that of high speed signal measurement technology until 2000.  He worked in opto-electronic sampling measurement technology as a guest researcher in National Physical Laboratory (NPL), Teddington, UK, from 1994 to 1995.  ETL was reorganized into National Institute of Advanced Industrial Science and Technology (AIST) in 2000.  He became a group leader of High Density Interconnection Group, Nanoelectronics Research Institute (NeRI), AIST.  He worked as a group leader specified for fundamental 3D LSI chip stacking technology in the national R&D project of High Density Electronic System Integration from 1999 to 2004.  He was a team leader of Opto-Electronic System Integration Collaborative Research Team, NeRI, from 2004 to 2009.  He has been a principal research scientist of NeRI  since 2009.  His present research field is high-speed high-density electronic packaging and interconnection technology including 3D LSI chip stacking and opto-electronic hybrid packaging.

Masahiro Aoyagi was awarded the Tsukuba prize of 1991 for the development of Josephson prototype computer ETL-JC1.  He has authored or co-authored 225 technical papers and has 80 patents. Masahiro Aoyagi has been an IEEE CPMT member since 1998.  He has been involved in the technical committee of Electronics Packaging Technology Conference (EPTC) held in Singapore and International Conference of Electronic Packaging (ICEP) held in Japan.  He was the chair of IEEE CPMT Japan Chapter from 2009 to 2010.

Masahiro Aoyagi holds memberships in Institution of Engineering and Technology (IET), International Microelectronics and Packaging Society (IMAPS), Society of Photo-Optical Instrumentation Engineers (SPIE), Institute of Electronics Information and Communication Engineers (IEICE), Japan Institute of Electronics Packaging (JIEP), Institute of Electrical Engineers of Japan (IEEJ), and Japan Society of Applied Physics (JSAP).